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  • How Meta’s Backend Aggregation (BAG) Powers Gigawatt‑Scale AI Clusters
  • How Meta’s Backend Aggregation (BAG) Powers Gigawatt‑Scale AI Clusters

    21 February 2026 by
    Suraj Barman

    Backend Aggregation (BAG) is the Ethernet‑based spine layer that interconnects regional spine fabrics, enabling Meta’s Prometheus AI cluster to reach gigawatt‑scale capacity.

    BAG Architectural Overview

    The BAG layer sits above the spine fabrics and below the global backbone, acting as a single point of aggregation for thousands of GPUs across multiple data‑center sites. It is built to support petabit‑class inter‑region links while keeping latency predictable.

    • Super‑spine topology: a mesh of high‑capacity links between BAG chassis in each region.
    • Inter‑BAG bandwidth up to 48 Pbps per region pair.
    • Distributed deployment reduces cable length to L2 edges, preserving shallow‑buffer switch performance.
    • Modular chassis host Jericho3 ASIC line cards for scalability.
    • eBGP with bandwidth attributes for dynamic path selection (see eBGP).

    Fabric Integration: DSF and NSF

    BAG connects two distinct L2 fabric families—Disaggregated Schedule Fabric (DSF) and Non‑Scheduled Fabric (NSF)—through dedicated edge pods in each building. This dual‑fabric approach balances scheduling flexibility with low‑latency traffic handling.

    • DSF zones use schedule‑aware switches for high‑throughput training workloads.
    • NSF zones rely on shallow‑buffer switches optimized for inference traffic.
    • Typical L2‑to‑BAG oversubscription ratio ~4.5:1, ensuring adequate headroom.
    • Spine Training Switches (STSW) are paired with each BAG plane for full mesh connectivity.
    • Oversubscription management guided by AI adoption best practices.

    Hardware Platform: Jericho3 ASIC Chassis

    The core of each BAG node is a chassis equipped with Jericho3 (J3) ASIC line cards, delivering massive port density and programmable pipelines.

    • Each line card provides up to 432 × 800 Gbps ports.
    • Supports both planar (direct‑match) and spread topologies.
    • Port striping and buffer allocation tuned for lossless congestion control (PFC).
    • Scalable power and cooling modules enable long‑term density growth.
    • Chassis design accommodates mixed‑length fiber runs for regional variance.

    Routing, Load Balancing, and Traffic Engineering

    Routing inside BAG uses eBGP with link‑bandwidth attributes, enabling Unequal Cost Multipath (UCMP) to spread traffic across multiple paths according to capacity.

    • UCMP automatically distributes flows based on link speed and policy weight.
    • Link‑state monitoring triggers fast failover within sub‑millisecond windows.
    • Conditional route aggregation reduces black‑hole risk during maintenance.
    • Automated draining of affected BAG planes ensures graceful traffic shift.
    • Integration with Zero‑Trust policies for end‑to‑end security.

    Security and Failure Resilience

    Security is enforced at the BAG layer using MACsec encryption, while a layered failure‑domain analysis protects against hardware, power, and fiber outages.

    • MACsec secures all BAG‑to‑BAG links against tampering.
    • Failure domains defined at BAG chassis, data‑hall, and power‑distribution levels.
    • Redundant power supplies and hot‑swap modules minimize downtime.
    • Automated health checks feed into Meta’s global observability platform.
    • Design supports graceful degradation, keeping GPU clusters operational during partial failures.

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